The present invention relates generally to a process for creating integrated circuit electronic devices. More particularly, the invention involves a process for forming refined CMOS class field effect transistor source/drain regions using a single photolithographic mask. The devices are formed to have metalized source/drain regions for p-channel field effect transistors and lightly doped drain (LDD) n-channel field effect transistor structures.
The use of selectively deposited tungsten to reduce the resistivity of source/drain regions is known to those who routinely practice in the art. Likewise, the configuration of n-channel field effect transistors with lightly doped drain (LDD) structures, which structures minimize transistor degradation due to hot electron trapping in the gate oxide layer, is known and selectively practiced. A representative discussion of the concepts and their application to the formation of field effect transistors appears in U.S. Pat. No. 4,503,601. The selective retention of metallic layers by forming silicides predates selective deposition of metal, and is known to generally involve a blanket deposition of the metal, a conditioning in a reactive environment to form silicides with exposed silicon, and a selective removal of metal which has not undergone reaction with exposed silicon. Those of skill in the art are also aware that sidewall dielectric layers may be created by anisotropic etching of a dielectric in the course of creating of lightly doped drain regions.
The prevailing practice of the prior art has been to create n-channel and p-channel transistors employing fabrication sequences which are relatively mirror images of each other, adjusted, for example, as to impurity concentration to offset the lower mobility of p-type regions and in structure to compensate for the relatively elevated susceptibility of n-channel transistors to the hot electron trapping phenomenon. Fundamental structural asymmetry between the two types of CMOS field effect transistors has not been ackowledged as a meaningful objective. In keeping with such practices of the prior art, multiple photolithographic masks are routinely used in operations practice after the patterning of the polysilicon gate electrodes merely to create the oppositely doped source/drain regions in self-alignment with the corresponding polysilicon gate electrodes. The processes which did eliminate the multiple masks commonly used lift-off techniques, techniques which are now disfavored by virtue of common negative experiences. Accordingly, there remains a need for a CMOS fabrication process which reduces the number of photolithographic masks, asymmetrically fabricates the p-channel field effect transistors to compensate in part for the higher resistivity of p-type source/drain regions, and asymmetrically forms the n-channel transistors in a configuration which minimizes hot electron trapping effects.